1. Technical Field
The invention relates to a programmable logic device, and in particular to a non-volatile memory cell for a programmable logic device.
2. Description of the Related Art
During the last few years, improvements in programmable logic device (PLD) architecture have permitted the manufacture of more complex devices while addressing the need for higher density and faster speeds. Despite these improvements, engineers still face certain problems and limitations with PLDs. One such problem is the volatility of the memory cells used in PLDs. Memory cells are typically used to store information regarding the configuration of a specific PLD.
FIG. 1 illustrates a conventional memory cell 100 which includes a latch 103 and an access transistor 104. Latch 103 includes two cross-coupled inverters 101 and 102. Memory cell 100 is programmed by bringing the signal on wordline WL high (i.e. a logic one) and providing the appropriate signal on bitline BL. For example, if the signal on bitline BL is low (i.e. a logic zero), then inverter 101 inverts that low signal and provides a logic one on output line OUT. Because of latch 103, the logic state of the output signal remains high until the cell 100 is reprogrammed by driving both signals on bitline BL and wordline WL to a logic high state. Alternatively, if power is lost or removed, the data stored by latch 103 is lost. Therefore, a need arises for a nonvolatile memory cell for use in PLDs that is capable of preserving data even in the event of a power loss.